1. Field of the Invention
This invention relates in general to threshold gates, and more particularly to asynchronous registers with embedded acknowledge collection.
2. Description of Related Art
Traditional logic systems, such as synchronous Boolean logic systems, typically employ clocking signals to regulate the sequential processing of binary logic signals. Typically, a digital logic circuit will respond to multiple inputs to generate an output. As input logic signals propagate through the sequential circuit, the sequential circuit output is unreliable for a period of time corresponding to worst case propagation delays through the individual logic gates. Typically, the output signal is sampled at a time when the output is stable, often by latching the output into a register. The sampling time is controlled by an independent clock source, i.e., one that is not derived from the states of the logic gates themselves.
Traditional Boolean logic has the disadvantage that it is not symbolically complete. Among its component elements, a traditional Boolean logic circuit exhibits time-dependent relationships, as well as symbolic-value-dependent relationships. The symbolic-value-dependent relationships depend on the interconnection of the logic gates. The time-dependent relationships depend on the propagation delay times of the logic gates. These two aspects of process expression are independent and require careful and explicit coordination to provide a complete and correct expression of a process. A carefully engineered Boolean logic circuit with its clock is a complete process expression, but it is not a symbolically complete expression.
While synchronous circuits have become the dominant logic class, a substantial amount of design time and analysis is necessary to avoid a variety of timing-related problems, such as race conditions and clock skew. Designers must build in timing margins to ensure that the circuit operates correctly which, in turn, decreases the maximum processing rate of the circuit. Furthermore, the fraction of power and die area that must be devoted to the clocking circuitry is substantial, and, in certain instances, has limited the total amount of circuitry that can be integrated onto a single chip.
The expression of both time-dependent and symbolic-value-dependent relationships can be integrated into an expression purely in terms of symbolic-value-dependent relationships with no external control expression. This expression is symbolically complete because it is completely expressed and completely determined solely in terms of symbolic-value-dependent relationships. A symbolically complete logic circuit has no time relationships and is completely insensitive to the propagation delays among its component elements. NULL convention logic provides a method for the design of symbolically complete logic circuits. A full description of NULL convention logic systems can be found in U.S. Pat. No. 5,305,463, which is incorporated here by reference.
NULL convention logic employs digital threshold gates to construct digital processing systems. Threshold gates serve as both data processing elements and data registration elements when used in NULL convention logic systems. A NULL convention asynchronous register regulates wavefront flow and interaction in sequential NULL convention circuits. NULL convention asynchronous registers produce an acknowledge signal, as well as accept incoming acknowledge signals. An incoming acknowledge signal contains information about the state of the next registration stage (the downstream circuit), while the outgoing acknowledge signal contains information about the state of the current registration stage. When the NULL convention asynchronous register receives a new acknowledge signal from the downstream circuit, the downstream circuit is ready to receive a new wavefront. Wavefronts alternate between meaningful data and NULL. Furthermore, the NULL convention asynchronous register produces a control signal which is used to request new wavefronts from the preceding circuit (the upstream circuit). A full description of NULL convention asyncronous registers can be found in U.S. Pat. No. 5,652,902, which is incorporated here by reference.
In many cases a single registration stage is acknowledged by two or more independent registration stages. In these cases, the multiple acknowledge signals must be collected and resolved to a single acknowledge signal using an explicit threshold gate. The resolved acknowledge signal is then passed to the single registration stage. The threshold gate performing the acknowledgement collection and resolution adds another processing stage which both increases the number of elements in the circuit and decreases the processing rate of the circuit.
It can be seen then that there is a need for acknowledgement collection and resolution within the NULL convention asynchronous registers.
It can also be seen that there is a need for asynchronous registers with embedded acknowledge collection for reducing the number of active elements required to perform acknowledgment collection and resolution, and for increasing the system processing throughput by reducing the number of processing stages.